Record carrier with alternating frames and interframe gaps

ABSTRACT

A digital recording and reproducing system, and record carrier for use with the system, in which frames and interframe gaps are recorded in a track on the record carrier. The record carrier has a plurality of longitudinally juxtaposed tracks which each comprises frames and interframe gaps alternating with one another longitudinally along that track. The interframe gaps of adjacent tracks are situated at substantially the same position, viewed in the longitudinal direction of the tracks, and adjacent interframe gaps have substantially the same lengths. In a first embodiment, the interframe gap directly following each frame in each track has substantially the same bit density as that frame. In a second embodiment, the interframe gaps in a track have varying lengths. The recording and reproducing system has recording device for recording the frames and interframe gaps on the record carrier, and a reproducing device for reading the frames from the track.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of application Ser. No. 07/669,136filed Mar. 13, 1991 and now issued as U.S. Pat. No. 5,267,098.

BACKGROUND OF THE INVENTION

The invention relates to a digital recording and reproducing system,and, in particular, a record carrier for use with that system. Morespecifically, the record carrier is of a type that can be used with asystem comprising a device for recording a digital electric signal in alongitudinal track on the record carrier and a device for reproducingthe digital electric signal from the track on the record carrier. Therecording device of such a system can receive the digital electricsignal with a specific sample rate, convert the digital electric signalinto a form in which it can be accommodated in consecutive frames at aspecific bit rate and record the frames in the track on the recordcarrier, thereby producing a record carrier having a longitudinal trackwith frames included therein. The reproducing device of such a systemcan read the frames from the track on the record carrier and decode theinformation contained in the frames to produce a digital electric signalhaving substantially the same sample rate.

A recording and reproducing system of the type described above (whichcan be used with a record carrier of the type described above); isknown, for example, from the book "The art of digital audio" by J.Watkinson, Focal Press 1988, Chapter 9. Chapter 9.20 of that bookdescribes, for example, a system, known as SDAT. In that system adigital signal is recorded in a plurality of juxtaposed tracks formed,or to be formed, on a record carrier in the longitudinal direction ofthe record carrier. The recording device in that system is intended forrecording a digital signal, such as a digital audio signal originatingfrom a digital signal source such as a Compact Disc (CD) audio player,on the record carrier. For that purpose, the digital signal having aspecific sample rate fs, which is fs=44.1 kHz if the digital source is aCD audio player, is applied to the recording device. In the recordingdevice, the digital electric signal is converted into a form in which itcan be recorded on the record carrier. Recording in the tracks iseffected at a bit rate which is neither equal to nor locked to thesample rate fs. For that purpose, the recording device comprises aseparate frequency source (crystal). However, a problem may arisebecause the sample rate at which the digital electric signal is appliedto the recording device varies. Moreover, the frequency supplied by thefrequency source may vary. The last-mentioned frequency variations maybe caused, for example, by temperature fluctuations affecting thefrequency source.

The recording device of the system described in the Watkinson book alsohas an analog input. An analog electric signal applied via that input issampled at a sample rate of 44.1 kHz and is digitized. In order toenable the analog signal to be sampled at 44.1 kHz, it is generallynecessary to have a second frequency source (crystal) to supply thesampling frequency of 44.1 kHz. However, the frequency supplied by thesecond source may also vary. If the digital signal is to be recordedcorrectly on the record carrier, the variations in the sample rate andthe clock frequency of the first-mentioned frequency source should beallowed and compensated for.

In the prior-art devices, this is realized, inter alia, by loading thesamples of the digital signal, which are received with a variable samplerate, into a memory and by reading them out of this memory at a fixedfrequency. Moreover, transport speed control is applied to compensatefor the variable bit rate with which the signal processor in therecording device supplies the information in the frames for recording onthe record carrier.

SUMMARY OF THE INVENTION

It is an object of the invention to propose a digital recording andreproducing system and in particular, a record carrier for use with thatsystem which in a different manner allows for the variations in thesample rate with which the digital signal is applied to the recordingdevice and the bit rate with which the information converted in thesignal processor is applied to the write head(s) of the recording devicefor recording.

In accordance with the invention, the recording device is adapted torecord frames alternately with interframe gaps in a track on the recordcarrier, and the reproducing device is adapted to read the framesalternating with interframe gaps. The interframe gaps as recorded in thetrack on the record carrier have a variable length. In addition theframes as recorded in the track on the record carrier may have avariable length.

The step underlying the invention is to refrain from correcting forvariations at the recording side. This means that the frames arerecorded on the record carrier alternately with an interframe gap havinga specific nominal length. Variations in the sample rate and the bitrate lead to variations in the length of the interframe gaps. Anincrease (decrease) of the sample rate relative to a nominal value ofthe sample rate (i.e., the 44.1 kHz) results in a smaller (larger)interframe gap and in a smaller (greater) length for the frame and asubsequent interframe gap. Moreover, an increase (decrease) of the bitrate relative to a nominal value for the bit rate leads to a larger(smaller) interframe gap, and the overall length of a frame and asubsequent interframe gap remains the same.

The fact that no correction for bit rate variations is applied duringrecording obviously does not mean that the recording device does notrequire tape transport speed control. A control system ensuring tapetransport with a fixed nominal tape speed is always needed. A correctionfor variations in the sample rate and the bit rate at the recording sideis now possible at the reproduction side by the variations in the lengthof a frame and a subsequent interframe gap on the one hand and by thevariations in the length of the interframe gap only on the other hand.At the reproduction side, the digital electric signal should, of course,be supplied with the sample rate of 44.1 kHz. For this purpose, thereproducing device comprises a frequency source supplying a frequencywhich is related to the sample rate of the digital electric signalappearing at the output of the reproducing device. This frequency sourcemay also supply a clock frequency which varies as a result of, interalia, temperature fluctuations to which the frequency source is subject.

This means that compensation for frequency variations must be applied atthe reproduction side. A compensation unit required for this purpose canbe used to compensate for the variations in the length of a frame and/ora (subsequent) interframe gap of the signal read from the recordcarrier.

The interframe gap may comprise channel bits which alternate with eachbit cell. This means alternately "zeros" and "ones". As already stated,the interframe gap should have a nominal length to enable the length ofthis interframe gap to be increased or reduced. Obviously, this nominallength depends on the nominal value of the sample rate of the digitalelectric signal applied to the recording device, on the nominal value ofthe bit rate with which the signal is eventually recorded on the recordcarrier and on percent variations relative to these nominal values.

In the present example, the nominal length of the interframe gaps isselected to be 64 channel bits. In the case of a maximum permissiblevariation of ±0.2% of the sample rate, the length of the interframe gapsthen varies between 32 and 96 channel bits. If after conversion andinsertion in the frames, the digital signal is recorded in a pluralityof longitudinally juxtaposed tracks on the record carrier, the frameswill be recorded in the tracks in such a manner that the interframe gapsof adjacent tracks are situated at substantially the same positions,viewed in the longitudinal direction of the record carrier, and adjacentinterframe gaps have the same length.

A record carrier in accordance with the invention has a plurality oflongitudinally juxtaposed tracks which each comprises frames andinterframe gaps alternating with one another longitudinally along thattrack. The interframe gaps of adjacent tracks are situated atsubstantially the same position, viewed in the longitudinal direction ofthe tracks, and adjacent interframe gaps have substantially the samelengths. In a first embodiment, the interframe gap directly followingeach frame in each track has substantially the same bit density as thatframe. In a second embodiment, the interframe gaps in a track havevarying lengths.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described in more detail, byway of example, with reference to the following Figures. In the Figures,

FIG. 1 shows an example of the recording device;

FIGS. 2a-2e illustrate the process of recording the information on therecord carrier depending upon variations in the sample rate and the bitrate;

FIG. 3 shows the device of FIG. 1 in more detail;

FIG. 4 shows an example of a reproducing device;

FIGS. 5a-5g illustrate the process of reading the information from therecord carrier depending upon variations in the sample rate, the bitrate and the length of the interframe gap;

FIG. 6 shows the reproducing device of FIG. 4 in more detail;

FIGS. 7a and 7b show some signal waveforms appearing in the reproducingdevice shown in FIG. 6;

FIG. 8 shows eight longitudinally juxtaposed tracks of a record carrierused in the invention, the tracks having frames and alternatinginterframe gaps recorded thereon; and

FIG. 9 shows the alternating bit logic values created from clock pulsesto form the interframe gap.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows diagrammatically an embodiment of the recording device inaccordance with the invention. The device comprises an analog input 1and a digital input 2. An analog audio signal, for example, generated bya microphone 3, can be applied to the device via the analog input 1. Inan analog-to-digital converter 5, the analog audio signal is sampled ata sample rate fs equal to 44.1 kHz, after which the samples aredigitized. For this purpose, clock pulses of a frequency equal to thesample rate fs are generated by a frequency source such as clockgenerator 6, which comprises a crystal operating at a frequency which isa multiple n of 44.1 kHz and which is applied to the clock signal input7 of the A/D converter 5. In the present example n is 512. The crystalthus operates at a frequency of 22.579 MHz.

A selector switch S1, which is in position c-b, transfers the samples toan input 8 of a coding unit, for example, subband coding unit (SBC) 9.Subband coding units are described comprehensively in the literature, sothat the subband coding unit will not be described in further detail.The samples from the A/D converter 5 are read into the subband codingunit 9 at a frequency corresponding to the sample rate fs. Therefore,the clock pulses from the clock generator 6 are applied to a clock pulseinput 10 of the subband coding unit 9 via a selector switch S2, which isin position c-b.

If a digital audio signal is applied to the input 2, the selectorswitches S1 and S2 are both in position a-b. By means of a phase-lockedloop (PLL) 25, the sample rate fs' is derived from the digital signal.The digital signal is read in at this sample rate fs' and is transferredto the subband coding unit 9.

Subband coded signals are applied to an output 11 of the subband codingunit and are transferred to an input 13 of a digital signal processingunit (or signal processor) 14 via line 12. The bit rate at which thesubband signals are applied to the signal processor 14 via line 12 is,for example, 384 kbit/s. In order to realize this, clock pulses of afrequency fp of m×48 kHz are generated in a clock generator 15 and areapplied to clock pulse inputs 16 and 17 of the subband coding unit 9 andthe signal processor 14, respectively. A bit rate of 384 kbit/s cannotbe derived simply from the clock generator 6, which has a crystaloperating at 512×44.1 kHz. For this purpose, clock generator 15 isemployed. Clock generator 15 has a crystal operating at m×48 kHz. In thepresent example m is also 512, so that the clock frequency of thecrystal is 24.576 MHz. The bit rate of 384 kbit/s can be derived simplyfrom frequency, namely via division by the number 64.

In the signal processor 14, the signal is converted, for example, in an8-to-10 converter into a modified signal. An 8-to-10 converter isdescribed, for example, in the Applicant's European Patent ApplicationNo. 150,082, to which U.S. Pat. No. 4,620,311 corresponds. In thisconverter, 8-bit data words are converted into 10-bit code words.Furthermore, the signal processor 14 can apply interleaving. All of thisserves to enable an error correction to be applied to the receivedinformation at the receiving side. Error correction as applied in thesystem described herein is described in the Applicant's prior EuropeanPatent Application No. 90200128.8, to which U.S. patent application Ser.No. 08/197,020, filed on Feb. 15, 1994 and now allowed, corresponds.

As a result of the processing, the information stream (and hence the bitrate) at the output 19 of the signal processor 14, i.e., the modifiedsignal, is larger than the information stream (bit rate) of the signalat the input 13. The information obtained from output 19 of the signalprocessor 14 is accommodated in frames. Subsequently, an interframe gapis inserted between every two successive frames. The length of theinterframe gap will appear to be variable; in the present example, thenominal value for the interframe gap In is taken to be 64 channel bits,which nominal value is subject to variations, as will become apparenthereinafter. The signal obtained by the signal processor 14 is suppliedto the output 19. The signal processor 14 converts the signal applied tothe input 13 in such a way that the bit rate at the output 19 is 768kbit/s, i.e., twice the bit rate at the input 13.

The output signal of the signal processor 14 is applied to an input 20of a write device 21, by means of which the signal is recorded in alongitudinal track on the record carrier 22. The write device 21 maycomprise one head or a plurality of heads, for example 8 juxtaposedheads, by means of which the information is recorded in 8 longitudinallyjuxtaposed tracks on the record carrier. See FIG. 8. In thelast-mentioned case, a signal having a bit rate of 96 (=768/8) kbit/s isapplied to each head.

A track contains frames having a fixed information content of 16320bits, alternating with interframe gaps having a nominal length of 64channel bits. This means that one frame and a successive interframe gapof nominal length situated in one track contain 16384 bits in total.This follows directly from the fact that in the present example theframe period is 1702/3 ms. In the case of an in-track bit rate of 96kbit/s, it follows that a frame including an interframe gap has anominal length of 16384 bits.

The sample rates fs and fs' may vary. Similarly, the frequency fp mayvary. As a result of this, there will be variations in the length of theinterframe gap (having a nominal length of 64 channel bits) in thetrack, the length of the frame (which always contains 16320 channelbits) in the track, the bit rate at the output of the signal processor14 (having a nominal value of 768 kbit/s), and the frame rate at theoutput of the signal processor 14 (having a nominal value of375/64=96000/16384 frames/s).

When it is assumed that the maximum permissible variation of the samplerate fs is 0.2%, this means that the overall length of a frame and asuccessive interframe gap in a track may exhibit a maximum variation of0.2% of 16384. This means a variation of 32 channel bits. Consequently,the interframe gap, which contains a nominal number of 64 channel bits,may have a length between 32 and 96 channel bits.

The operation of the device will now be described in more detail withreference to FIGS. 2a-2e.

FIG. 2a illustrates a situation in which there are no variations in thesample rate fs, i.e., fs is equal to the nominal sample rate fsn, and inthe clock frequency fp, i.e., fp is equal to the nominal clock frequencyfpn. On the upper line in FIG. 2a, the nominal program cycles in thesignal processor 14 are represented as a function of time. The nominalprogram cycles comprise nominal program blocks Pn and intervals T2. Thelower line in FIG. 2a represents the nominal data stream as recorded ina track on the record carrier as a function of time, it being assumedhereinafter that eight of these tracks extend parallel adjacent oneanother on the record carrier. See FIG. 8. Each track comprises nominalframes Fn and interframe gaps In having lengths of Ta and Tb,respectively. Since the record carrier is moved at a constant speed thislower line also represents the physical position of the nominal datastream in the track on the record carrier.

The nominal program blocks Pn in the signal processor 14 have a lengthT1. Between two nominal program blocks, a nominal time interval T2 isinterposed. In a program block Pn, the signal processor 14 prepares thedata for recording: i.e., interleaving, Reed-Solomon coding, and 8-10modulation.

In a program block Pn, the signal processor 14 processes the informationcontained in 2048 information packets (slots) of 32 bits each, which aresupplied by the subband coding unit 9. As already stated, a doubleamount of information is produced at the output of the signal processor14, i.e., 2048×32×2=131072 bits. These bits are divided among 8 tracksand are stored in these tracks. This means 16384 bits per track.However, the storage of the actual information requires only 16320 bitsper track, as already stated above. This information is stored in onenominal frame Fn in the track. The signal processor 14 interposesnominal interframe gaps In between the nominal frames Fn, which nominalinterframe gaps In have a nominal length of 64 (=16384-16320) channelbits. At a bit rate of 96 kbit/s, this means that the length of thenominal interframe gap In in time Tb is 0.66 ms. This means that theconnection between the output 19 of the signal processor 14 and theinput 20 of the write device 21 in fact comprises eight signal lines forthe transfer of the 8 signals to be recorded in the eight tracks. Thenominal frames Fn are recorded in the tracks in such a manner thatadjacent nominal interframe gaps In in the eight tracks all have thesame length, i.e., Tb. The same applies to the adjacent nominal framesFn in the eight tracks, i.e., they have a length of Ta. See FIG. 8.

FIG. 2b illustrates a situation in which the sample rate fs deviatesfrom the nominal value in such a manner that fs>fsn. This means that thecrystal in the clock generator 6 of FIG. 1 operates at a frequencyhigher than n×44.1 kHz. All of the other parameters remain the same.Since fp has not changed, the processing time in the program block Premains the same (i.e., P=Pn) and is consequently equal to T. Similarly,the bit rate at which the information is recorded in the track remainsthe same. This means that the length of the frames F, viewed in time, isequal to the nominal length Ta of the frames. Since fs>fsn theinformation stream applied to the input 8 of the subband coding unit 9of FIG. 1 is larger. Nevertheless, the device processes this largerinformation stream. Eventually, this results in a larger informationstream to be recorded in the track. This is achieved in that the programcycles succeed one another more rapidly. The intervals between theprogram blocks in FIG. 2b designated T2' are smaller than the nominalintervals T2 in FIG. 2a. Moreover, the frames F succeed one another morerapidly, i.e., the frame rate has increased. This is realized at thesame bit rate by making the interframe gaps smaller (I<In). Thus, thesignal processor 14 inserts interframe gaps of a length smaller than 64channel bits in such a way that after processing the increasedinformation stream on the input 8 of the subband coding unit 9 can berecorded in the track on the record carrier. This will be explainedlater in conjunction with reference to FIG. 3. However, it is to benoted here that variations in the crystal frequency n×44.1 kHz of theclock generator 6 affect the rate of information transfer between thesubband coding unit 9 and the signal processor 14 and, in addition,affect the starting instants of the signal processing in the programblocks P in the signal processor 14. This effect is representeddiagrammatically by means of the broken line 26 in FIG. 1 and will beexplained in conjunction with reference to FIG. 3. The variations of fsand fs' are applied to the clock generator 6 and the signal processor 14via the switch S3, which should be in the appropriate position, and theline 26.

FIG. 2c illustrates the situation in which the sample rate fs is smallerthan fsn, the other parameters again being the same. Since fp is againequal to fpn, the program blocks P again have a length of T1 and the bitrate at which the information is recorded in the track is unchanged.This means that the length of the frames F is equal to the nominallength Ta.

Since fs<fsn, a smaller information stream is applied to the input 8 ofthe subband coding unit 9 of FIG. 1. This means that a smallerinformation stream is to be recorded in the track. The program cyclesnow succeed one another less rapidly. The intervals between the programblocks of P are then larger, i.e., T2">T2. Moreover, the frame rate isreduced. This is achieved at the same bit rate by inserting longerinterframe gaps (I>In) between the frames. Thus, the signal processor 14inserts interframe gaps of such a length that, after processing, theinformation stream at the input 8 of the subband coding unit 9 can berecorded in the track. Consequently, the interframe gaps become longerthan 64 channel bits.

FIG. 2d illustrates a situation in which the clock frequency fp ishigher than the nominal clock frequency fpn, and the sample rate fs isequal to fsn. The processor 14 now operates at a higher clock frequency.The program blocks P are now shorter than T1. Moreover, the bit rate atwhich the information is recorded in the track increases.

Since the information stream applied to the input 8 of the subbandcoding unit 9 corresponds to the nominal information stream (fs is equalto fsn) the frame rate remains equal to the nominal frame rate of 375/64frames/s. Moreover, the overall cycle time in the signal processor 14,i.e., T1'+T2'" remains equal to the nominal cycle time, i.e., T1+T2.

In the case of a higher bit rate of the information stream on the recordcarrier an equal frame rate means that the physical length of the framesin the track becomes smaller (F<Fn) and that the length of theinterframe gaps increases (I>In) in such a way that Ta'+Tb'=Ta+Tb. Theinterframe gaps now contain more than 64 channel bits.

FIG. 2e illustrates the situation in which the clock frequency fp issmaller than the nominal clock frequency fpn. In this case the samplerate fs is equal to fsn. The processor 14 now operates at a lower clockfrequency. The program blocks P are now longer than T1. Moreover, thebit rate at which the information is recorded in the track decreases.

In the same way as in the situation illustrated in FIG. 2d the framerate now also remains equal to 375/64 frames/s. The total program cycletime, T1"+T2"", is again equal to the nominal cycle time T1+T2. Thismeans that the intervals are smaller, T2""<T2.

In the case of a lower bit rate of the information stream on the recordcarrier the equal frame rate results in an increased physical length ofthe frames in the track F>Fn, and a reduced length of the interframegaps (I<In), in such a way that Ta"+Tb"=Ta+Tb. From the above, it alsofollows that the length of the interframe gap as recorded in a track onthe record carrier is related to the ratio between fs and fp. If fs andfp both increase or decrease, while their ratio remains the same, thelength of the interframe gap will not change. This can be demonstratedin qualitative terms by comparison between FIG. 2b and FIG. 2d.

The operation of the device shown in FIG. 1, for obtaining the outputsignals as illustrated in FIG. 2, will now be explained with referenceto FIG. 3.

FIG. 3 shows the clock generator 6, which comprises a crystal 31operating at a frequency of 512×44.1 kHz, i.e., 22.5792 MHz. In adivider 32, which forms part of the clock generator 6, this frequency isdivided by 512, yielding a frequency fs which is 44.1 kHz in the nominalsituation. It is obvious that in the case of a frequency source such asPLL 25 of FIG. 1, this source should comprise a PLL operating at a(nominal) frequency of 512×44.1 kHz. For simplicity, however, thecircuit shown in FIG. 1, including the switch S1, is not shown in FIG.3. The 22.5792 MHz clock frequency is applied to a counter 33 via afrequency divider 32A, which divides the frequency of the crystal 31 byfour.

The clock generator 15 in FIG. 1, as shown in FIG. 3, comprises acrystal 34 operating at a frequency of 512×48 kHz, i.e., 24.576 MHz.This clock frequency is applied to a counter 35 via a frequency divider37, which divides the frequency of the crystal 34 by N. In the nominalcase N is 4, as will become apparent hereinafter.

In a comparator 36 the counts of the two counters 33 and 35 are comparedwith each other in the following manner. The counters 33 and 35 are both10-bit counters. Counter 33 counts cyclically from 0 to 881 inclusiveand the counter 35 counts cyclically from 0 to 959 inclusive. Bothcounters are started at the same instant and have a start value of zero.When the counter 35 reaches the count "0" (decimal) the count of thecounter 33 is used for determining N in the divider 37. If this count issubstantially "0" (decimal) N in the divider 37 is set to 4. If thecount of the counter 33 has not reached the value "0" at that time, Nwill be taken equal to 6. If the count of the counter 33 is larger than"0", this results in N=3. After this, the cycle is restarted, the valuefor N obtained in a preceding cycle being stored in the divider 37, andthe counter 33 is not reset to zero but continues counting starting fromthe value reached previously. In this way a phase-locked loop has beenrealized in which f_(i) is locked in phase to f_(s). In this way thecomparator 36 each time compares the count of the counter 33 with thevalue 882 and supplies a signal A to define the value N in a manner asdescribed above.

When both crystals 31 and 34 operate at their nominal values N will be4. A frequency f equal to 6.144 MHz then appears on the output 39.

A variation of the clock frequency of the crystal 31 in a positive sense(i.e., the crystal supplies a clock frequency higher than 22.5792 MHz)means a higher count of the counter 33 and hence another value of thecontrol parameter A, i.e., such as to decrement the value of N in thedivider 37. The clock frequency f_(i) supplied by the divider 37 is thenhigher than 6.144 MHz. A variation of the clock frequency of the crystal31 in a negative sense then means that the clock frequency supplied bythe divider 37 is lower than 6.144 MHz. On an average, a variation inthe clock frequency of the crystal 34 will not result in a long-termvariation in the clock frequency fi of the divider 37. Nevertheless, theclock frequency at the input 38 increases. For the generation of thecontrol parameter A, an increase of the clock frequency of the crystal34 (while the frequency of the crystal 31 remains the same) has the sameeffect as in the case in which the clock frequency of the crystal 31decreases (while the frequency of the crystal 34 remains the same). Thismeans that the value N in the divider increases. Over a longer periodthese two effects substantially cancel one another. Therefore, it may beconsidered to derive fi only from the clock frequency of the crystal 31.However, preferably this is not done because deriving fi directly fromthe clock frequency of the crystal 31, without allowing for the clockfrequency of the crystal 34, requires the use of inconvenient anddifficult to realize dividing factors.

The nominal value of 6.144 MHz for fi can be derived simply from theclock frequency of the crystal 34, namely by a division by four.Moreover, variations in the clock frequency of the crystal 34, asexplained hereinbefore, do not affect fi. In addition, the variations inthe clock frequency of the crystal 31 result in variations of fi, as isdesired.

The clock signal from the divider 37 is applied to a divider 71, whichdivides the clock frequency by 512 so that a clock signal of a nominalfrequency of 12 kHz appears on the output. This 12 kHz frequency isapplied to subband coder 9' and to processor 14'. This frequency definesthe data transfer between the subband coder 9' and the processor 14' andthe data rate at which this transfer takes place. This is because this12 kHz frequency dictates the frequency at which the information packetsof 32 bits length are transferred to the processor 14' by the subbandcoder 9' via the connection 12. This results in a data transfer rate of384 kbit/sec. For a further explanation of the format of the signalapplied to line 12 by the subband coder 9' reference is made to theprior Netherlands Patent Applications 89 01 401 and 90 00 338, to whichU.S. Pat. No. 5,323,396 corresponds. This 12 kHz frequency is alsoapplied to a divider 72, which divides the clock frequency by 2048. Thisyields a nominal clock frequency of 375/64 at the input 73. This clockfrequency dictates and is equal to the frame rate, and it is applied tothe processor 14'.

The 24.576 MHz clock frequency from the crystal 34 is also applied tothe processor 14' via a divider 74, which divides the clock frequency byfour.

The processor in FIG. 3 bears the reference numeral 14' to indicate thatit represents that section of the signal processor 14 which performs thesignal processing upon the information stream. Consequently, the signalprocessor 14 in FIG. 1 comprises the processor 14' and some peripheralparts, such as some of the counters and frequency dividers shown in FIG.3. In fact, the same applies with respect to the subband coding unit 9of FIG. 1, a portion of which bears the reference numeral 9' in FIG. 3.

The clock frequency of nominally 6.144 MHz from the divider 74 is alsoapplied to a divider 75, which divides the clock frequency again by 128,so that a clock frequency of 48 kHz is generated on the output. Theoutput of this divider 75 is coupled to the c-terminal of a switch S2.The output 76 of the processor 14' is coupled to the a-terminal of theswitch S2. The processor 14' further has an output 77 on which a controlsignal is produced which is applied to the control signal input of theswitch S2. The b-terminal of the switch S2 is coupled to the output 19.

The device operates as follows. Again, it is assumed that all theparameters have their nominal values as illustrated in FIG. 2a. The datais read in at 44.1 kHz, is processed in the subband coder 9' and isloaded into the processor 14' at a bit rate of 384 kbit/s. This iseffected under control of the 12 kHz clock frequency from the divider71. The clock frequency from the divider 72 dictates the startinginstants t1, t3, t5, see FIG. 2a, of the program blocks Pn, in which theinformation applied to the signal processor 14 is processed. Thefrequency fj from the frequency divider 74 dictates the operating speedin the processor 14' and thus determines the length (t1, t2) of aprogram block Pn. In a program block Pn, a fixed amount of informationis processed in conformity with a fixed algorithm, so that the frequencyfj from the divider 74 dictates the length of the program block Pn. Assoon as a fixed amount of information has been processed, i.e., at theinstant t2, which is ascertained internally in the processor 14', theprocessed information is output via the output 76. The processor 14'again ascertains internally when all the information has been suppliedto its output. This is at the instant t6, see FIG. 2a, the lower line.In the time interval t2, t6 the switch S2 is position a-b, so that theinformation from the processor 14' can be applied to the output 19. Atthe instant t6, the processor 14' generates an IFG control signal on theoutput 77, under the influence of which signal the switch is set toposition c-b, see FIG. 1. This IFG control signal remains available onthe output 77 until the processor 14' has internally ascertained thetermination of the next program block Pn at the instant t4, so that theIFG control signal disappears again. In the time interval t6, t4, inwhich the switch S2 is consequently in position c-b, clock pulses havinga frequency of 48 kHz and supplied by the divider 75 are applied to theoutput and, as such, creates the interframe gap. In the nominalsituation, there are 32 clock pulses which effectively createalternating bit logic values in the interframe gap. See FIG. 9.Consequently, the time interval t6, t4 has a nominal length of 0.66 ms.At the instant t4, another program block is carried out. The amount ofinformation processed in this program block, during the time intervalt3, t4, is applied to the output 76 and is transferred to the recordingdevice 21 via the switch S2, which is again in position a-b. In therecording device, the information is recorded on the record carrier inthe time interval Ta following t4.

FIG. 2b illustrates the situation in which fs is higher than 44.1 kHz.This is because the frequency of the crystal 31 is higher than 22.5792MHz. This means that the information appears on the input 8 of thesubband coder 9' at a higher sampling frequency and is consequentlyprocessed at a higher clock frequency, i.e., with a higher speed, inthis subband coder 9'. The frequency at the output of the divider 71 isnow higher than 12 kHz. This also means that the data transfer rate tothe processor 14' is now higher than 384 kbit/s. The frequency generatedby the divider 72 is also higher. This means that the program blocks Psucceed one another more rapidly. This can be seen in FIG. 2b in thatthe time interval t1, t7 is smaller than the time interval t1, t3 ofFIG. 2a. Since the frequency fj, which is applied to the input 17 of theprocessor 14' and which dictates the speed of the signal processing inthe processor 14' has not changed, the processing time in the processor14' has not changed. Viewed in time, the length of the program blockshas remained the same as in the situation illustrated in FIG. 2a. Theprocessor 14' again internally detects the instants t2, t8 at which thefixed amount of information has been processed, so that it can beapplied to the output. The switch S2 is in position a-b, so that theinformation can be transferred to the output 19. The processor 14'further detects the instant t6 at which the information is applied tothe output 76. At this instant, the IFG control signal is appliedinternally to the output 77, so that the switch S2 is set to positionc-b and the 48 kHz clock pulses from the divider 75 can be applied tothe output 19 to produce the interframe gap. At the instant t8, theprocessor 14' detects the end of the next program block. At this instantthe IFG control signal is terminated, so that the switch S2 is reset toposition a-b. The information processed in the next program block canthen be applied to the output 19. The recording time t2, t6 for theinformation in the record carrier is equal to the recording time in FIG.2a. Since the total time of a program cycle t2, t8 is smaller than inFIG. 2a, the interframe gap is consequently shorter.

The description of the operation of the circuit in the situationillustrated in FIG. 2c can now be given briefly. If fs is smaller than44.1 kHz, the speed of information processing in the subband coder 9'and the speed of data transfer to the processor 14' is lower. Moreover,the frequency supplied to the processor 14' by the divider 72 is lower.The clock pulses from divider 72 dictate the beginnings of the programblocks at the instants t1, t11, t13, see FIG. 2c. The time interval t1,t11 is now longer than the time interval t1, t3 of FIG. 2a. However, thesignal processing in the processor 14' has not changed. This means thatthe switch S2 is in position a-b during the time interval t2, t6 and inposition c-b in the time interval t6, t12.

FIG. 2d now illustrates the situation in which the clock frequency fpfrom the crystal 34 is higher than 24.576 MHz. As stated hereinbefore,these variations do not affect the clock frequencies supplied by thedividers 71 and 72. However, the clock frequency supplied by thefrequency divider 74 changes. This clock frequency increases. This meansthat the speed of signal processing in the processor 14' has increased.The length of the program blocks P has consequently become shorter. InFIG. 2d this is visible in that the time intervals t14, t2 and t15, t4are shorter than the time intervals t1, t2 of FIG. 2a. The pulses fromthe frequency divider 72 again dictate the beginnings of the programblocks at the instants t14, t15, t16. The time intervals t14, t15 andt15, t16 are equal to the time interval t1, t3. This is because thecrystal 31 again has its nominal frequency value and the variation inthe resonant frequency of the crystal 34 has no effect.

At the instant t2, the operation in program block P has ceased and theinformation can be applied to the output 76 of the processor 14'. Sincefp is now larger than the nominal value fpn the information is suppliedmore rapidly to the output 76. This means that the information processedin a program block is recorded more rapidly and hence in a shorter timeinterval t2, t17, on the record carrier. In FIG. 2d this is visible inthat the time interval t2, t17 is shorter than the time interval t2, t6of FIG. 2a.

At the instant t17, the processor 14' again produces the IFG controlsignal on the output 77, causing the switch S2 to change over toposition c-b. At this instant, the clock pulses from the frequencydivider 75, which form the interframe gap, are recorded on the recordcarrier. Since the frequency of the crystal 34 is higher than thenominal value of 24.576 MHz, the frequency of the clock pulses suppliedby the divider 75 will be higher than 48 kHz. The bit rate of the datasupplied to the output 76 by the processor 14' and recorded on therecord carrier is now higher than the nominal bit rate of 96 kbit/s pertrack.

FIG. 2e illustrates the situation in which the clock frequency fp of thecrystal 34 is lower than 24.576 MHz. Again this variation has no effecton the clock frequencies supplied by the frequency dividers 71 and 72.However, the clock frequencies supplied by the frequency dividers 74 and75 change, i.e., they decrease. This means that the speed of signalprocessing in the processor 14' is lower. Consequently, the length ofthe program blocks P is greater than the nominal length. In FIG. 2e thisis visible in that the time intervals t18, t2 and t19, t4 are longerthan the time interval t1, t2 of FIG. 2a. The pulses from the frequencydivider 72 again dictate the instants t18, t19, t20 at which the programblocks P begin. The time intervals t18, t19 and t19, t20 are equal tothe time interval t1, t3.

At the instant t2, processing in the program block P is completed andthe information can be supplied to the output 76 of the processor 14'.Since fp is now smaller than the nominal value fpn the information issupplied more slowly to the output 76. This means that the informationprocessed in a program block is recorded more slowly, i.e., in a longertime interval t2, t21, on the record carrier. In FIG. 2e this is visiblein that the time interval t2, t21 is shorter than the time interval t2,t6 in FIG. 2a. At the instant t21, the processor 14' again produces theIFG control signal on the output 77, so that the switch S2 is set toposition c-b.

Since the frequency of the crystal 34 is lower than the nominal value of24.576 MHz, the frequency of the clock pulses supplied by the frequencydivider 75 becomes smaller than 48 kHz. Moreover, the bit rate of thedata transferred to the output 76 by the processor 14' and recorded onthe record carrier is lower than the nominal bit rate of 96 kbit/s in atrack.

FIG. 4 shows diagrammatically an embodiment of the reproducing device inaccordance with the invention. The device comprises a reading device 40,comprising at least one read head 41, for reading the informationrecorded by the write device 21 of FIG. 1 from a track on a recordcarrier 22. If the record carrier 22 again comprises a plurality oftracks which are juxtaposed in the longitudinal direction on this recordcarrier, for example, 8 tracks, the reading device will comprise 8 readheads 41. The serial data stream read from the track (tracks) is appliedto a signal processing unit (or signal processor) 43 via the line 42. Inthis signal processor 43 the information contained in the frames isprocessed inversely to the manner in which the information has beenprocessed in the signal processor 14 shown in FIG. 1. This means thatdeinterleaving and an error correction can be applied, and that the10-bit channel words are reconverted into 8-bit information words in a10-8 converter. This yields the subband signals, which are applied fromthe output 44 to a decoder unit 46, in the present case subband decoderunit 46, via the line 45. In this subband decoder unit 46, the subbandsignals are recombined to form a wide-band digital signal. Thiswide-band digital signal is applied to the output 47 and, via the line48, to the input 49 of the digital-to-analog converter 50. The devicecomprises a first frequency source such as clock generator 51, whichsupplies a (nominal) clock frequency fp to a clock signal input 52 ofthe signal processor 43 and to a clock signal input 53 of the subbanddecoder unit 46. In this case, fp is equal to m×48 kHz or 24.576 MHz.The clock frequency at which the program in the signal processor 43 runsis derived from fp. In addition, the (nominal) bit rate of 384 kb/s withwhich the information is applied to the subband decoder unit 46 via theline 45 is also derived from this frequency fp.

The reproducing device further comprises a second frequency source suchas clock generator 54, which generates a nominal sampling frequency fsand supplies it to a clock signal input 55 of the subband decoder unit46 and to a clock signal input 56 of the D/A converter 50. Thisfrequency fs is 44.1 kHz and is the frequency with which the samples areapplied to the D/A converter. For this purpose, the frequency divider 54comprises a crystal operating at a frequency of n×44.1 kHz, where n isagain 512, so that the crystal operates at a frequency of 22.5792 MHz.Subsequently, an analog signal appears on the output 57. The devicefurther comprises a speed control for the tape transport. This speedcontrol comprises a synchronizing-signal detector 60, a phase comparator61, a frequency converter 62 and a control device for controlling thetransport speed of a motor 63 by means of a control signal which isgenerated by the phase comparator 61 and is applied to the motor via aloop filter 64A, comprising an integrator. The motor 63 drives a capstan64 which cooperates with a pressure roller 66 to provide the transportof the record carrier 22.

By means of the sync detector 60, a frequency signal related to theframe rate FR (in frames/s) of the signal being read is derived from thesignal read from the record carrier. The frame rate FR can be derivedfrom the serial output signal supplied by the reading device 40 in amanner as described with reference to FIG. 6. By means of the frequencyconverter 62, a frequency FR' which is in a fixed relationship to thedesired frame rate is derived from the clock frequency m×48 kHz from thefrequency source 51. For deriving the frequency FR', the frequencyconverter 62 also receives the frequency fs of n×44.1 kHz from the clockgenerator 54, via the line 68.

Variations of fs influence the value FR'. If fs has exactly the nominalvalue of 44.1 kHz, FR' will be a multiple of the nominal frame rate of376/64. However, variations of the frequency m×fp do not result invariations of FR'. In the comparator 61, the two frequencies FR and FR'are compared with each other. From the difference, a control signal isderived for controlling the motor speed, and hence the transport speedof the record carrier, via the line 64. The operation of the deviceshown in FIG. 4 will be described in more detail with reference to FIG.5.

FIG. 5a pertains to the nominal situation. This means that the samplerate fs is exactly equal to the nominal value fsn (=44.1 kHz), the clockfrequency fp is exactly equal to the nominal value fpn (=24.576 MHz),the interframe gaps on the record carrier have exactly their nominallength of 64 channel bits, and the frame rate FR is exactly equal to thenominal frame rate FRN of 375/64 frames/s. The tape transport is theneffected at a speed Vt equal to the nominal transport (or read) speedVn. FIG. 5a, therefore, in fact corresponds to FIG. 2a. The upper linerepresents the serial data stream of the frames alternating with theinterframe gaps in the time sequence in which they are read. SinceVt=Vn, this means that this line also represents the physical positionof the nominal frames Fn and the nominal interframe gaps In on therecord carrier. The second line in FIG. 5a shows the nominal programcycle comprising program blocks Pn of a length T1 and intervals of alength T2.

FIG. 5b represents the situation in which the sample rate fs produced bythe frequency source 54 is higher than the nominal sample rate fsn, theother parameters being unchanged. Since fp has not changed theprocessing time in the program block P remains the same (i.e., P=Pn) andis consequently T1. The higher sample rate for the samples applied tothe D/A converter 50 means that a larger data stream is applied to thisD/A converter 50. This also means that a larger data stream is to beread from the record carrier 22.

A control signal is generated on the line 64 such that the transportspeed Vt increases (Vt>Vn). The frames Fn thus recorded on the recordcarrier as illustrated in FIG. 5a are now read at a faster rate. This isrepresented by means of the upper line in FIG. 5b. This line indicateshow the information read from the record carrier is applied to thesignal processor 43, as a function of time.

As is apparent from FIG. 5b, the frames now succeed each other morerapidly (Ta'+Tb'<Ta+Tb). Similarly, the program blocks, which basicallyhave the same length as in FIG. 5a, now succeed one another more rapidlyviewed in time (T2'<T2). Consequently the program cycle is shorter. Boththe frame rate and the bit rate of the signal read from the recordcarrier are higher than the nominal frame rate and the nominal bit rate,respectively. It is obvious that the transport speed is increasedexactly as much as is necessary to allow for the increased data streamat the input of the D/A converter 50.

FIG. 5c illustrates the situation in which fs is smaller than thenominal sample rate fsn, the other parameters being unchanged. In thesame way as in FIG. 5b, the processing time in the program blocks Premains the same, i.e., T1, fp is equal to fpn. The lower frequency atthe input 49 of the D/A converter 50 means that the data stream at thisinput 49 is smaller than the nominal data stream at this point. Thisalso requires a smaller data stream on the line 42. Consequently, acontrol signal is generated on the line 64 such that the transport speedVt of the record carrier 22 is reduced (Vt<Vn). The frames, which havebeen recorded on the record carrier 22 in a manner as illustrated inFIG. 5a, are, therefore, read with a delay. This is represented by theupper line in FIG. 5c. The frames now succeed each other more slowly(T"+Tb">Ta+Tb). Similarly, the program blocks P succeed one another moreslowly (T2">T2). Both the frame rate and the bit rate in the signal readfrom the record carrier 22 are, therefore, smaller than the nominalframe rate and the nominal bit rate, respectively. Again the reductionof the transport speed of the record carrier is exactly as much as isnecessary to allow for the reduced data stream at the input 49 of theD/A converter 50.

FIG. 5d illustrates a situation in which only the clock frequency fpdeviates from the nominal value, i.e. fp>fpn. Since fs is equal to fsnthe transport speed Vt remains equal to the nominal transport speed Vn.The information read from the record carrier, see the upper line in FIG.5d, is the same as in the situation illustrated in FIG. 5a. Only theprogram blocks P are shorter (T1'<T1). However, the total program cycledoes not change (T1'+T2'"=T1+T2).

FIG. 5e illustrates the situation in which fp<fpn. In that case, theprogram blocks P are longer, i.e., T1">T1. Conversely, the intervals aresmaller, i.e., T2""<T2. However, the total program cycle has notchanged: T1"+T2""=T1+T2.

FIG. 5f illustrates a situation in which the interframe gaps on therecord carrier are larger than the nominal interframe gaps, i.e., I>In.An interframe gap on the record carrier being larger than the nominalinterframe gap can be obtained in two ways, namely in that duringrecording fs<fsn, see FIG. 2c, or in that during recording fp>fpn, seeFIG. 2d.

Starting from the situation of FIG. 2c, in which the frames have beenrecorded on the record carrier in such a way that the overall length ofa frame and an interframe gap on the record carrier is greater than thenominal length, the motor control in the reproducing device will be suchthat the read time for one frame and one interframe gap correspondsexactly to the nominal read time Ta+Tb. This means that the transportspeed is increased (vt>vn). Since the frame length on the record carrierin FIG. 2c is equal to the nominal frame length, this means that duringreading at a speed vt>vn the read time Ta'" for a frame is smaller thanthe nominal read time Ta. This means that the read time Tb'" for theinterframe gaps during reading is longer than the nominal read time Tbfor the interframe gap. This is illustrated in FIG. 5f.

Starting from the situation of FIG. 2d, in which the frames andinterframe gaps are arranged on the record carrier in such a manner thatthe total length of a frame and an interframe gap is exactly equal tothe nominal length Ta+Tb, this means that during reproduction thetransport speed Vt of the record carrier is selected to be equal to thenominal transport speed vn.

During reading, the data stream, therefore, comprises frames of a lengthsmaller than the nominal frame length and an interframe gap of a lengthgreater than the nominal interframe gap length. This is exactly asillustrated in FIG. 2d. The data stream being read, as represented bythe upper line in FIG. 5f, consequently also applies to the reproductionof a signal recorded in a manner as illustrated in FIG. 2d. The programblocks have a duration equal to the nominal program duration T1, becausefp is equal to the nominal clock frequency fpn.

FIG. 5g represents the situation in which a record carrier is read withframes and interframe gaps such that the length of the interframe gap onthe record carrier is smaller than the nominal interframe gap length.This is the situation as illustrated in FIGS. 2b and 2e.

In the situation as illustrated in FIG. 2b, where the total length of aframe and an interframe gap is smaller than the nominal length, themotor control of the reproducing device will control the motor transportin such a way that the total read time for a frame and an interframe gapbecomes equal to the nominal read time Ta+Tb, see FIG. 5a. This meansthat the transport speed vt is smaller than the nominal transport speedvn. Since the length of the frame in FIG. 2b is equal to the nominalframe length, this means that the read time for a frame is greater thanthe nominal read time Ta and the read time for an interframe gap issmaller than the nominal read time Tb.

In the situation illustrated in FIG. 2e, the total length of a frame andan interframe gap on the record carrier is equal to the nominal length.During reading, the transport speed of the record carrier will,therefore, be equal to the nominal transport speed. This means that theread time for the frame is longer than the nominal read time Ta and thatthe read time for an interframe gap is smaller than the nominal readtime Tb.

In both of these previously discussed cases, a situation as illustratedby the upper line of FIG. 5g is obtained. Since the clock frequency fpis equal to the nominal clock frequency fpn, the duration of the programblocks is equal to the nominal program duration T1.

It is evident that variations of the crystal frequency, n×44.1 kHz ofthe generator 54 influence the speed of information transfer between thesignal processor 43 and the subband decoder unit 46, and also influencethe starting instants of the signal processing in the program blocks inthe signal processor 43, see FIGS. 5b and 5c. This influence isindicated diagrammatically by a broken line in FIG. 4 and will beexplained with reference to FIG. 6.

FIG. 6 shows the reproducing device of FIG. 4 in greater detail, theoperation of the device, as already illustrated by means of FIG. 5,being described in more detail. The circuit shown in FIG. 6 comprisesmany parts also used in the circuit shown in FIG. 3. In FIG. 6, theseparts bear the same reference numerals but primed.

The operation of the parts bearing primed reference numerals isidentical to the operation of the corresponding parts in FIG. 3. Thismeans that the frequency divider 71' supplies a nominal frequency of 12kHz, which nominal frequency is not influenced by variations of thefrequency of the crystal 34' but is affected by variations of thefrequency of the crystal 31'. Variations in the frequency of the crystal31' in a positive sense (the value increases) result in a higherfrequency at the output of the divider 71' and variations in a negativesense (the frequency of the crystal 31' decreases) result in a lowerfrequency at the output of the divider 71'. The frequency of divider 71'dictates the bit rate of the information transfer between the processor43' and the subband decoder 46'. In the nominal situation this bit rateis again (12,000×32)=384 kb/s.

The device further comprises a counter 80, a sampler 81 and the syncdetector 60, as also shown in FIG. 4. The counter 80 and the sampler 81together constitute the phase comparator 61 in FIG. 4.

The counter 80 is an 8-bit counter which, under the influence of theclock pulses supplied by the crystal 34', counts from 0 to 255, afterwhich it is restarted. At the instant at which a frame starts, whichinstant is dictated by a clock pulse supplied by the frequency divider72', the counter 80 is set to a specific starting value, after whichthis counter proceeds to count under the influence of the clock pulsesfrom the crystal 34'. This is illustrated in FIG. 7a. FIG. 7a shows thatthe appearance of a pulse from the divider 72', indicated by "strtfrm",causes the counter to be set to the count "56" (decimal). The reason forthis will become apparent hereinafter.

The sync detector 60 is adapted to derive the sync words from the serialinformation stream being read. These sync words are the block sync wordsin the signal. Each frame of the information signal as recorded on therecord carrier comprises a plurality of frame blocks. Netherlands PatentApplication No. 9001038, to which U.S. Pat. No. 5,148,330 correspondsstates that a frame in a track comprises 32 frame blocks. Each blockcomprises 51 10-bit words. Consequently, a frame comprises 32×510=16,320bits in total. Each block comprises one block sync word. Consequently,the detector 60 detects 32 block sync words in a frame. FIG. 7b showsthe output signal of the detector 60. The detector 60 generates 8 pulsesper frame at the output. In fact, this means that the detector 60detects every fourth block sync word, upon which it produces a pulse onits output.

Each time a pulse from the detector 60 appears on its input 83 thesampler 81 takes over the count of the counter 80 applied to its input84 and generates a control signal corresponding to this count, whichsignal is applied, via line 64, to the motor 63 for driving the capstan65. In the nominal situation, i.e., the frequencies of the crystals 31'and 34' and the interframe gap length on the record carrier all havetheir nominal value and the pulses in FIG. 7b are situated at suchinstants that the count is stored in the sampler 81 halfway between thecounts 0 and 255 (decimal), i.e., the count 127 or 128. The controlsignal on line 64 is such that the motor control corrects the transportspeed of the record carrier to be exactly equal to the nominal speed vn,see FIG. 5a, so that the actual frame rate FR corresponds exactly to thedesired frame rate FR', see FIG. 4.

The instant at which a frame begins, which is the instant of the firstSTRTFRM pulse in FIG. 7a, and the initial count to which the counter 80should then be set, should of course be such that at a clock frequencyof 12 kHz, with which the counter 80 is driven after the frequencydivision by 2048 in the divider 95, the counter has reached the count127 or 128 at the instant at which the first pulse appears on the outputof the block sync detector 60, i.e., the first pulse P1 in FIG. 7b. Thepulses STRTFRM generated by the divider 72' dictate the instants t1, t2,t3, see FIG. 5a. If the information read from the record carrier isadequate to enable the signal processing in the processor 43' to bestarted, which is at the instant t4, this signal processing is continueduntil the entire operation in a program block is completed. This is atthe instant t2. At this instant, the processor 43' starts to acceptinformation of a subsequent frame, so that processing of thisinformation can be started at the instant t5.

It is to be noted that in the present case, the processor bears thereference numeral 43' and the subband decoder bears the referencenumeral 46'. The reason for this is that the unit 43' forms that sectionof the signal processor 43 which performs the signal processing upon theinformation stream. This means that the processor 43 in FIG. 4 comprisesthe section 43' and some peripheral devices, such as some of thecounters and frequency dividers shown in FIG. 6. The same applies withrespect to the subband decoder 46' of FIG. 6 which is a portion of thesubband decoder unit 46 of FIG. 4.

For the following example, it is assumed that fs>fsn. This means thatthe crystal 31' operates at a higher frequency than 22.5792 MHz, seeFIG. 5b. As a result of this, the frequency of the pulses on the outputof the divider 72' increases. Therefore, the STRTFRM pulses succeed oneanother more rapidly. This means that the counter 80 is reset to theinitial count sooner and that upon the next pulse, which is the pulse P1in the signal shown in FIG. 7b, the count of the counter 80 is higherthan 127 or 128. The sawtooth curve shown in FIG. 7a does not changedbecause the counter 80 is driven with a frequency derived from thecrystal 34' which still operates at its nominal value. Thus, on line 64,a control signal is generated which causes the transport speed toincrease until the pulses of FIG. 7b appear at instants averaged overone frame for which the counts at the instants of the pulses P1 in FIG.7b, which are now spaced more closely in time, are 127 or 128. Thismeans that at the instants at which the pulses P1, P2, P3, P4 appear thecounts are larger than 127 or 128 and at the instants at which thepulses P5, P6, P7 and P8 appear the counts are smaller than 127 or 128.In more general terms, this means that the counts decrease each time atthose instants at which the successive pulses P1 to P8 appear within twoconsecutive STRTFRM pulses. Since the motor control is an integratingcontrol, see the loop filter 64A in FIG. 4, the transport speed at theincreased speed vt (>vn) is maintained and the count of the counter 80remains 127 or 128 averaged over a (plurality of) frame(s).

Consequently, the frames as well as the interframe gaps are read withina shorter time. This is illustrated by the upper line in FIG. 5b. Thetime interval of t1, t6 of FIG. 5b is shorter than the time interval t1,t2 of FIG. 5a. Since the processor 43' is operated at a nominalfrequency of 6.144 MHz, the signal processing performed in a programblock takes the same time as in the nominal situation.

For this example, it is assumed that fs<fsn, see FIG. 5c. This meansthat the crystal 31' operates at a frequency below 22.5792 MHz. Thefrequency divider 72' now supplies the STRTFRM pulses at a frequencylower than the nominal frequency of 375/64. This means that viewed intime the counter 80 is reset to the initial count at a later instant andthat upon the next pulse, which is the pulse P1, in the signal shown inFIG. 7b the count of the counter 80 is smaller than 127 or 128. Acontrol signal is generated on line 64, which signal ensures that thetransport speed is reduced until the pulses shown in FIG. 7b, which arenow spaced further apart viewed in time, appear at instants in a framefor which the counts average 127 or 128. This means that at the instantsat which the pulses p1, p2, p3 and p4 appear the counts are smaller than127 or 128, while at the instants at which the pulses p5, p6, p7 and p8,appear the counts are larger than 127 or 128. This is because viewed intime the sawtooth curve shown in FIG. 7a has not changed since thecrystal 34' operates at its nominal frequency. In more general terms,this means that the counts each time increase at those instants of thesuccessive pulses p1 to p8 which appear within two consecutive STRTFRMpulses. Since the motor control is an integrating control, the transportspeed is maintained at the reduced speed vt (<vn) and, averaged over a(plurality of) frame(s), the count is 127 or 128 at the samplinginstants represented by the instants at which the pulses from the syncdetector 60 appear.

Thus, the frames as well as the interframe gaps are read from the recordcarrier over a longer time. This is illustrated by the upper line inFIG. 5c. The time interval t1, t10 of FIG. 5c is longer than the timeinterval t1, t2 of FIG. 5a. Since the processor 43' is operated at thenominal frequency fpn of 6.144 MHz, the signal processing performed in aprogram block P takes as much time as in the nominal situation.

For this example, it is assumed that fp>fpn, see FIG. 5d. This meansthat the spacing between the STRTFRM pulses has not changed. This isbecause variations of fp do not influence the frequency supplied by thedividers 71' and 72'. On account of the higher clock frequency appliedto the counter 80, the sawtooth shown in FIG. 7a, viewed in time, has ahigher frequency. Averaged over one frame, the counts at the instants atwhich the pulses pl to p8 appear, will again be 127 or 128. This meansthat the counts at the instants at which the pulses p1, p2, p3 and p4appear are smaller than 127 or 128 and the counts at the instants afterthe pulses p5, p6, p7 or p8 are larger than 127. In more general terms,this means that the counts each time increase at those instants at whichthe successive pulses P1 to P8 appear within two consecutive STRTFRMpulses. Averaged over a (plurality of) frame(s) the count of the counter80 remains 127 or 128. The transport speed of the record carrier thenremains equal to the nominal transport speed vn.

A similar line of reasoning applies to the situation for which fp<fpn,see FIG. 5e. Viewed in time, the sawtooth shown in FIG. 7a has nowslowed down. This means that the counts at the instants at which thepulses p1, p2, p3 and p4 appear are larger than 127 or 128 and thecounts at the instants at which the pulses p5, p6, p7 and p8 appear aresmaller than 127 or 128. In more general terms, the counts each timedecrease at those instants at which the successive pulses P1 to P8appear within two consecutive STRTFRM pulses. However, averaged over a(plurality of) frame(s) the counts are still 127 or 128 at a transportspeed equal to the nominal transport speed Vn.

In FIG. 5f, the interframe gap on the record carrier is larger than thenominal interframe gap. In the situation illustrated in FIG. 2c, theframes, including the interframe gap on the record carrier, appear to belonger than the nominal length. Since the sawtooth shown in FIG. 7a hasnot changed and the STRTFRM frequency has not changed, the average countof the counter 80 in the case of a nominal transport speed duringreading would be too high for one frame period (higher than 127 or 128).The transport speed is then increased so that averaged over a (pluralityof) frame(s) the count is again 127 or 128. However, in a situation asillustrated in FIG. 2d the counts during reading at the nominaltransport speed are already 127 or 128 averaged over a (plurality of)frame(s). Thus, the nominal transport speed is maintained. Starting fromboth situations, this means that a signal is read as illustrated in FIG.5f by the upper line.

In FIG. 5g, the interframe gap length on the record carrier was smallerthan the nominal interframe gap length. If this relates to a situationsuch as the one illustrated in FIG. 2b, the frames, including theinterframe gaps, on the record carrier appear to be shorter than thenominal length. Since the sawtooth shown in FIG. 7a has not changed andthe STRTFRM frequency has also remained the same, the average count ofthe counter 80 at a nominal transport speed during reading would be toolow for a (plurality of) frame(s). Therefore, the transport speeddecreases so that the average count again becomes 127 or 128. However,in the situation of FIG. 2e, the counts during reading at the nominaltransport speed are already equal to 127 or 128 averaged over one frameperiod. Consequently, the nominal transport speed is maintained.

It is to be noted that the invention is not limited to the embodimentsdisclosed herein. Various modifications of the embodiments described arepossible without departing from the scope of the invention as defined inthe appended claims.

I claim:
 1. A record carrier having a plurality of longitudinallyjuxtaposed tracks which each comprises frames and interframe gapsalternating with one another longitudinally along that track, theinterframe gap directly following each frame in each track havingsubstantially the same bit density as that frame, the interframe gaps ofadjacent tracks being situated at substantially the same position,viewed in the longitudinal direction of the tracks, and adjacentinterframe gaps having substantially the same lengths.
 2. The recordcarrier as claimed in claim 1, wherein the interframe gaps in a trackhave varying lengths.
 3. The record carrier as claimed in claim 1,wherein the frames in a track have varying lengths.
 4. The recordcarrier as claimed in claim 1, wherein each of the interframe gapscomprises channel bits with logic values which alternate one after theother.
 5. The record carrier as claimed in claim 1, wherein theinterframe gaps have a nominal length of 64 channel bits.
 6. The recordcarrier as claimed in claim 1, wherein the interframe gaps have lengthswhich vary between 32 and 96 channel bits.
 7. A record carrier having aplurality of longitudinally juxtaposed tracks which each comprisesframes and interframe gaps alternating with one another longitudinallyalong that track, the interframe gaps of adjacent tracks being situatedat substantially the same position, viewed in the longitudinal directionof the tracks, adjacent interframe gaps having substantially the samelengths, and the interframe gaps in a track having varying lengths. 8.The record carrier as claimed in claim 7, wherein the frames in thetrack have varying lengths.
 9. The record carrier as claimed in claim 7,wherein each of the interframe gaps comprises channel bits with logicvalues which alternate one after the other.
 10. The record carrier asclaimed in claim 7, wherein the interframe gaps have a nominal length of64 channel bits.
 11. The record carrier as claimed in claim 7, whereinthe interframe gaps have lengths which vary between 32 and 96 channelbits.
 12. A record carrier having a plurality of longitudinallyjuxtaposed tracks which each comprises frames and interframe gapsalternating with one another longitudinally along that track, theinterframe gaps of adjacent tracks being situated at substantially thesame position, viewed in the longitudinal direction of the tracks,adjacent interframe gaps having substantially the same lengths, and theframes in a track having varying lengths.
 13. The record carrier asclaimed in claim 12, wherein the interframe gaps in the track havevarying lengths.
 14. The record carrier as claimed in claim 12, whereineach of the interframe gaps comprises channel bits with logic valueswhich alternate one after the other.
 15. The record carrier as claimedin claim 12, wherein the interframe gaps have a nominal length of 64channel bits.
 16. The record carrier as claimed in claim 12, wherein theinterframe gaps have lengths which vary between 32 and 96 channel bits.